Click all four cells. Three of them are zero, but a plain processor doesn't know that until it looks.
Most teams bolt on hardware and hope. Ours runs the same job on the plain processor and on a sparse neural-network unit, on one FPGA board, and counts every cycle of both.
Pick a workload and press run. The chip with fewer cycles always reaches the flag first. Step by step slows the faster chip down a little so you can watch it hop between nonzeros; real cycle ratio runs both on one clock with no mercy. The cycle counters are the same either way.
Visits every weight, zero or not. No setup, no waiting, just a lot of math.
Stores and visits only the nonzeros, but has to be set up, fed, and waited on.
Press run to start the race.
Four steps. The accelerator only does math in step three. The other three are the price of asking someone else to do your work, and most benchmarks quietly leave them out.
The processor writes the job into the accelerator's control registers and tells it to go.
Weights and the input cross the shared bus. The sparse path moves fewer weights but adds indices and row pointers.
Multiply-adds. The processor does one per weight. The NPU reads a pointer, jumps to the next nonzero, and runs several lanes at once.
Wait for the done signal, then carry the result vector back over the bus.
Every phase, both chips, from your last run. Pink is overhead that does no math.
| phase | processor | sparse npu | relative |
|---|---|---|---|
| total cycles | — | — |
An inspectable platform for deciding when acceleration pays off, built first for BU ECE teaching labs. Everything needed to rerun the experiment ships with it.